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MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
DESCRIPTION
The M65675FP/M65676FP is a NTSC/PAL encoder LSI that converts CCIR 601 or CCIR 656 (SMPTE125M) format digital video signals into analog component and composite video signals in accordance with either NTSC or B/G-PAL standards. The 10-bit digital luma (Y) and analog chroma (U/V) signals are available in Y/U/V output mode. In addition it performs the closed caption capability (TV line 21/ NTSC), CGMS*1 encoding (TV line 20/NTSC), WSS*2 encoding (TV line 23/PAL), Macrovision copy protection *3 function (Rev. 7.01) and on-screen display. The OSD function can be directly accessed by the OSD microprocessor via built-in interface.
* *
* * *
Controllable Picture Processing Functions Color, TINT and Brightness Built-in Analog Functions Y/C Mixing Two 10-bit DACs Three 6-dB Amplifiers Built-in 27 MHz System Clock Generator Single 3.3V Supply 64-pin PQFP Package
Note *1: Copy Generation Management System-A (IEC1880) *2: Wide Screen Signaling (ETS300 294) *3: This applies to M65675FP only. This device is protected by U.S. patent number 4631603, 4577216 and 4819098 and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intend for home and other limited pay-par-view use only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. *4: Y output is 10bit digital signal.
FEATURES
* * * * * * * * * * *
NTSC and B/G-PAL Outputs Component Y/C (S-Video), Composite (CVBS) or Y *4/U/V Outputs Supporting CCIR601, CCIR656 (SMPTE125M) Format Data Processing Y/Cb/Cr and Y/U/V Pixel Data 27MHz Clock Frequency (Two-times Oversampling) Macrovision Copy Protection*3 Processing (Revision 7.01) Close Captioning Supporting (line 21/NTSC) (ODD Parity Operation) V-Code Supporting (line 21/NTSC) (ODD Parity Operation) CGMS*1 Data Insertion (line 20/NTSC) (CRCC Error Correction Code Operation) WSS*2 Supporting (line23/PAL) OSD Insertion Interface and 384-bit Color Look-up Table
APPLICATION
DVD Players, Digital Satellite & Cable System (Set Top Boxes/ IRDs), Video CD, Multimedia Terminals, Video Games, Digital VCR & Camcoder etc.
PIN CONFIGURATION (TOP VIEW)
42 Ccomp
CVBS
DAC
DAY
Cref
Yref
C in
Y in
44 AVDD1
45 AVSS1
38 AVDD2
36 AVSS2
34 N.C.
40 N.C
41
39
46
43
37
35
Ycomp 49 N.C. 50 DVDD1 51 DVSS1 52 X out X in
53 54
48
47
33 32 N.C. 31 N.C. 30 DVDD1 29 28 27 26
C
Y
TEST SCL SDA ACK RESET Master/slave OSD2 OSD1 OSD0 OSDCK
DVSS2 55 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0
56 57 58 59 60 61 62 63
M65675FP M65676FP
25 24 23 22 21 20
19 DVSS1 18 DVDD1 17 DVDD2 10 11 12 13 14 15
DVDD2 64 DVSS2 16
5 8 3 4 6
DVSS2 1
2
DVASEL
VD9
VD8
7
VD7
VD6
9
VD5
VD4
VD3
VD2
VD1
PXCLK
Outline 64P6N-A
VD0
HD
VD
NC : NO CONNECTION
1
OSD2 OSD1 OSD0 LPF DAY AVSS1 AVDD1 Y ref C ref AVSS2 AVDD2 BPF Yin Cin DAC Video signal generator Y/Cb/Cr Encoder Y Y/U 6dB C-sync adder CGMS/WSS Manager 10bit DAC C/V Closed Caption Manager 10bit DAC Y Burst adder Video Anti Copy signal adder (1) Y/U/V
OSDCK
BLOCK DIAGRAM
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
Input Interface
OSD Interface
Clamp & bias Y
Y
PXD [7:0]
Blanking control Interpolation filter
OSD controller
Y Cb/U
6dB
C
OSD mixer U V sub carrier generator Chroma Encoder
Demulti Plexer
Cb/U
PXCLK
CLK generator Analog
Xout Xin
Oscillator
HD control register signal generator
Sync Processing
Cb/Cr Interpolation filter
VD [9:0] Cr/V Cb/Cr to U/V Converter
8-color Look-up table RAM
Converter
Video Anti Copy signal adder (2)
Cr/V
Y/C MIX
6dB CVBS
Anti Copy Processing 1
VD
HD/VD generator
Muster /Slave
C-sync generator
Timing pulse generator
serial interface 1: This function bloc is M65675FP only
Commands register
slave receiver
M65675FP/M65676FP
MITSUBISHI ICs (TV)
DIGITAL NTSC/PAL ENCODER
TEST
SCL
RESET
DVSS2(X2) DVSS1(X2)
DVDD1(X2)
DVDD2(X2)
ACK
SDA
2
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VO Ta Tstg Parameter DC supply voltage Digital input voltage Digital output voltage Operating temperature Storage temperature Min. -0.3 -0.3 -0.3 -20 -40 Limits Typ. Max. 4.5
VDD+0.3 VDD+0.3
Unit V V V C C
+25
+75 +125
RECOMMENDED OPERATING CONDITION (Ta=25C, DVDD=AVDD=3.3V, DVSS=AVSS=0V, unless otherwise noted)
Symbol Parameter Test conditions Min. 3.0 3.15 0 0 DVDD=3.0V DVDD=3.6V DVDD=3.0V, VI=0V or VI=3.6V f=1MHz, VDD=0V 0 2.5 7 Limits Typ. 3.3 3.3 Max. 3.6 3.45 45 55 0.8 3.6 15 15 0.05 3.25 7 4.0 15 10 Rref=2.2k, RL=300 Rref=2.2k , RL=300 000 to 3FF 1.5 7.5 5.50 5.10 0.8 1.6 10 6.00 6.00 11.5 6.50 6.85 2.0 1.0 15 Unit
Supply Digital supply voltage DVDDX AVDDX Analog supply voltage DIDD Digital current consumption AIDD Analog current consumption Digital input VIL Input voltage VIH IIL Input leakage current CI Input capacitance Digital output VOL Output voltage VOH CO Output capacitance I2C bus IO Output current IOZ Output leakage current (off) D/A converter Res Resolution INL Integral non-linearity error DNL Differential non-linearity error VfSMAX Maximum output amplitude 6-dB amplifier Rbias Bias resistor GV_YC Voltage gain (Y/C) GV_CV Voltage gain (CVBS) DRin Input dynamic range DRout Output dynamic range
V V mA mA V V A pF V V pF mA A Bit LSB LSB V P-P k dB dB VP-P VP-P
DVDD=3.3V, | IO |<1A f=1MHz, VDD=0V DVDD=3.0V, VIL=0.4V DVDD=3.6V, VI=0V or VI=3.6V
3
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Synchronization Control Block C-sync and several timing control signals for internal use are generated with 3 different H/V sync signals as reference. 1st reference H/V sync signal is external input, 2nd is internally generated one and 3rd is decoded one in digital blanking code (SAV, EAV etc.) Serial Interface Block The registers can be read and written according to I 2C bus format. The data transport to the internal blocks is performed on the trailing edge of V-sync, except for some set-up registers. Analog Signal Processing Block The output of the 10-bit DAC is 1.2VP-P at the sampling frequency of 27.0MHz. The inputs of Yin and Cin are set up to 0.6VP-P (Typ) and the component outputs will be amplified by 6-dB up to 1.2VP-P (Typ). The analog composite signal from the mixing circuit is also amplified up to 1.2VP-P (Typ)
M65675FP/M65676FP System Architecture Block Diagram of M65675FP/M65676FP
The M65675FP/M65676FP block diagram is shown in Fig. 3.1. The M65675FP/M65676FP consists of 4 functional blocks: a video signal processing, a synchronization control, a serial interface and an analog signal processing blocks. The video signal processing block includes an input interface, OSD interface, YCbCr to YUV converter/encoder and copy protection signal generator (This function block is M65675FP only). A sync generator and timing pulse generator are in the synchronization control block. The serial interface block has an I 2C slave register and command register. The analog signal processing block includes two 10-bit DACs, a Y/C mixing circuit and three 6-dB amplifiers.
General Description of Each Functional Blocks
Video Signal Processing Block The Y/Cb/Cr or Y/U/V are converted into digital Y/C signals in accordance with either NTSC and B/G-PAL standards. In addition the closed caption, CGMS/WSS and copy protection signals will be inserted in that digital Y/C signals. [Input Interface] The multiplexed Y/Cb/Cr or Y/U/V pixel data are divided by the individual components, then the Cb/Cr or U/V data rate is increased from 6.75 Mbps up to 13.5Mbps. [OSD Interface] The digital video signal in the CLT (Color Look-up Table) is overlaid with OSD data according to the external instructions. [Y/Cb/Cr to Y/U/V Converter] It converts the Y/Cb/Cr into Y/U/V, and then c-sync and burst signals are inserted on the converted Y and U/V signals, respectively. However, the burst insertion is not done in the Y/U/V output mode.
Functional Description Video Signal processing Input Interface Input Format
The video encoder accepts 16/8-bit CCIR601 and CCIR656 format. The specifications of these format are described as follows; 16-bit CCIR601 Interface PXCLK=13.5MHz Y=8-bit/13.5Mbps 16-235 straight-binary-data Cb/Cr=8-bit/13.5 Mbps (Cb=Cr=8-bit/6.75 Mbps) 16-240 128 offset-binary-data Active video area 525/60=720-pixel480 line/frame (22/284 line-263/525 line) 625/50=720-pixel576 line/frame (23/336 line-310/623 line) 8-bit CCIR601 Interface
[Encoder] The closed caption, CGMS/WSS and copy protection signals are inserted into the Y signal and C signal is modulated into the appropriate standards. After that processing, both Y and C signals will be oversampled. [Copy Protection Processing] According to the copy protection setting, VBI pulse (AGC and backporch pulse) and Advanced Split Burst are generated in accordance with Macrovision Rev 7.01.
PXCLK=27.0MHz Cb/Y/Cr=8-bit/27.0Mbps Y= 8-bit/13.5Mbps 16-235 straight-binary-data Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75Mbps) 16-240 128 offset-binary-data Active video area 525/60=720-pixel480 line/frame (22/284 line-263/525 line) 625/50=720-pixel576 line/frame (23/336 line-310/623 line)
4
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
CCIR656 Interface PXCLK=27.0MHz Cb/Y/Cr=8-bit/27.0Mbps Y=8-bit/27.0Mbps 16-235 straight-binary-data Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75 Mbps) 16-240 128 offset-binary-data Active video area 525/60=720-pixel480 line/frame (22/284 line-263/525 line) 625/50=720-pixel576 line/frame (23/336 line-310/623 line) Vertical blanking Interval 525/60=1/264-9/272 Digital field 1 (ODD)=4-265 Digital field 2 (EVEN)=266-3 625/50=624/311-22/335 Digital field 1 (ODD)=1-312 Digital field 2 (EVEN)=313-625 Horizontal blanking Interval525/60=276CLK (0H=32CLK) EAV=1-4CLK/SAV=273-276CLK 625/50=288CLK (0H=24CLK) EAV=1-4CLK/SAV=285-288CLK The input data (X), except the active data in the above support format, are clipped as shown below; 8/16-bit CCIR601 Interface Y : X16 AE 16 X235AE235 Cb/Cr : X16 AE 16 (U/V) X240AE240 (Whole period) (Whole period)
OSD Interface Color Look-up Table (CLT)
The built-in CLT can be equivalent to 4bit8 colors, so that the reproduced colors are 8/4096. The setting ranges and the signal levels in the overlaying of Y, Cb and Cr each are shown below; Y : Setting range=1 (h) to F (h) : straight-binary data Signal Level=10 (h) to F0 (h) : straight-binary data Cb/Cr : Setting range=1 (h) to F (h) : 8 offset-binary data Signal level=10 (h) to F0 (h) : 128 offset-binary data
OSD Control
Overlaying the appointed data on the video signal from MPEG is possible by inputting the address data to the CLT in synchronization with OSDCLK, H-sync and V-sync. The overlaying is prohibited in case CLT address is set to 7 (h). The OSD control specifications are shown below; OSDCLK= selectable 13.5MHz or 6.75MHz selectable continuous or discontinuous (pausing during H-sync) clock Color Signal Blend=Maximum 3 colors are allowed to be set. The data of CLT addresses 0 (h) to 2 (h) are dedicated to color blending. The blend ratio is fixed by 1:1 and blend mode is selectable between Y/Cmix and Ymix mode.
Y/Cb/Cr to Y/U/V Converter C-sync Addition
The sync signal, set up in the register, is added to Y signal according to C-sync timing generated from H-sync/V-sync. Typical sync height, set up in the register, is calculated by the following
CCIR656 Interface Y : X16 AE 16 X235AE235 X (U/V) AE 16 Cb/Cr : X16 AE 16 X240AE240 X AE 128 (Active video period) (Blanking period) (Active video period) (Blanking period)
equations; Sync level={(White peak input level-16)2.5Xsync (IRE)}/100 In the case of NTSC : {(235-16)2.540}/100=219 (DBH) PAL : {(235-16)2.543}/100=235.4 (EBH)
Note: Xsync=Output sync level (IRE)
Digital Multiplexing
The input pixel data described in 4.1.1.1 are de-multiplexed, then Y, Cb,Cr and Y, U, V signals will be converted to each 8-bit parallel data. After the above conversion, 6.75Mbps Cb, Cr/U, V data are interpolated at a double clock rate of 13.5Mbps.
Set-up Control (NTSC)
In the NTSC signal generation mode, three set-up modes are possible according to the register. Selectable set-up modes are; Mode 0 : Set-upAE0 IRE Mode 1 : Set-upAE+7.5 IRE Mode 2 : Set-upAE-7.5 IRE
PXCLK Processing
PXCLK is generated from the 27.0MHz system clock according to the appropriate selected format and the clock signal for Y, Cb, Cr/Y, U, V data de-multiplexing is also generated.
Cb/Cr to U/V Conversion
The Cb/Cr data are converted into the U/V data by the following equations; U=0.493Cb/0.564 V=0.877Cr/0.713
5
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Burst Insertion
The burst signal, set up in the corresponding register, is inserted to Cb/Cr according to the burst timing signal. The burst signal is derived from the following equations; NTSC=ABS (Burst level-128)5/5.47 (IRE) Ex. 40IRE=54H PAL={ABS (Burst level-128)5/5.47}/2 (IRE) Ex. 43IRE=5EH
Encoder Closed Caption Encoding
In the NTSC (525/60) mode, 8-bit2byte data, including parity bit, set in the register are converted into the format shown in fig. 1 and then will be inserted in the video signal according to the register data of the closed captions control specification (closed caption on/ off and caption data insertion mode). After the completion of transmission, the new data are loaded in the register by setting the close caption flag to "1", then the transferred data are loaded in the register on the trailing edge of V-sync pulse by setting that flag to "0". (In case the closed caption flag is "1", the new data loading is halted and the caption data are not inserted in the video signals).
Video Anticopy Signal Addition [1] (VBI Amplitude/CSP)
This applies to M65675FP only. Sync-amplitude function and Color StripeTM control function are carried out according to the corresponding register, in accordance with Macrovision Video Anti Copy Process Rev. 7.0 dated September 6 1996.
7 cycles of 503kHz (Clock Run-in ) Color Burst
Parity Bit 1st. byte
Parity Bit 2nd. byte
START BIT CCD00
CCD03
CCD04
CCD05
CCD06
CCD07
CCD10
CCD11
CCD12
CCD13
CCD14
CCD15
CCD01
CCD02
33.764s 12.910s 3.972+0.2/-0.0s
51.268+0.2/-0.0s 10.5000.5s 61.3310.5s 63.556s 20(283) line 21(284) line 22(285) line
Fig. 1 CLOSED CAPTION WAVEFORM
CCD16 CCD17
6
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
CGMS (IEC 1880) Encoding
In the NTSC (525/60) mode, the 20-bit data, consisting of 14-bit data including CRCC code and 6-bit error correction code generated by the input data, are converted into the video format
shown in fig. 2 and then inserted in TV line 20/283, according to the register data of CGMS control mode (CGMS on/off). The transferred data are loaded to the register on the trailing edge of V-sync, after a write-enable (WE) was set to "1".
Ref Bit Input Data CRCC
Color Burst
2.23250s
49.10.3s 11.20.3s 63.556s 19(282) line 20(283) line 21(284) line
Fig. 2 CGMS WAVEFORM
WSS (ETS 300 294) Encoding
In the PAL (625/50) mode, 14-bit data, set in the register, is modulated to the signal format shown in fig. 3 and then will be inserted into TV line 23, according to the register data of WSS
control mode (WSS on/off). The new register data are loaded on the trailing edge of V-sync, after a write-enable (WE) was set to "1".
"0"
7010 IRE "1" 20010ns 24line
bit 10
bit 11
bit 12
bit 13
bit 14
bit 15
bit 16
bit 17
bit 18
bit 19
Run in
Start code
Input Data 20010ns
Color Burst
Aspect Ratio (4bit)
Enhanced Subtit- Others Services les (3bit) (3bit) (4bit)
11.00.25s
27.41.4s 64.0s
22 line
23 line
Fig. 3 WSS WAVEFORM
7
500mV5%
1F1C71C7 1E3C1F
group1
group2
group3 group4
bit 20
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
bit 9
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Samples will then be sent to customer after MITSUBISHI's confirmation of it. Sales Orders In case the customer has a Macrovision license: The customer provides MITSUBISHI Electric Corp. with a written confirmation of the license. Customer can then purchases M65675FP. In case the customer does not have a Macrovision license: The customer must obtain a license or waiver from Macrovision. The customer must provide MITSUBISHI Electric Corp. with a written confirmation of the license or waiver from Macrovision. Customer can then purchases M65675FP.
Color Subcarrier Generation
32-bit accuracy color subcarrier is generated from 27-MHz clock signal according to the register data. The subcarrier frequencies are as follows; M-fsc mode=455fH/2 =3.579545MHz10Hz B-fsc_1 mode =1135fH/4 =4.433593755Hz B-fsc_2 mode =1135fH/4+25Hz =4.433618755Hz
Note:The above carrier frequencies are based on the input clock frequency of 27.0MHz. So, the generated subcarrier is also fluctuated according to a drift of the external clock frequency.
Interpolation
The 13.5MHz data of Y, U and V are processed by an avarage-value interpolation and then each data rate are increased up to two times that of 27.0MHz.
Synchronization Control Sync Signal Processing
The H/V sync signals are available in following 3 conditions; (1) in synchronization with external sync signal, (2) in a slave mode which refers to a digital blanking code and (3) in a master mode which refers to a internally generated sync signal, according to the register data. The timing specifications in each modes are as follows; The slave mode H-sync input condition: 1H =63.555 - 1.5/+10ms (525/60) =64.0 - 1.5/+10ms (625/50) V-sync input condition : 1V =262.5H10H (525/60) =312.5H10H (625/50) Field condition : Even-1/4HChroma modulation
The selected subcarrier frequency, which generated 27.0MHz rate U and V signals, is modulated.
Video Anticopy Signal Addition [2] (Pseudo Sync/AGC/Back Porch Pulses)
This applies to M65675FP only. The several anticopy signals (Pseudo Sync/AGC/Back Porch Pulses), in accordance with Macrovision Video anticopy processes Rev.7.01 dated Sep. 6, 1996, are inserted into the appropriate video signals according to the register data. (This applies to M65675FP only)
Video Anticopy Signal Generation
This applies to M65675FP only. Several anticopy signals in accordance with Macrovision anticopy processes Rev. 7.01 dated Sep. 6, 1996 are added to Y/C output signals according to the I2C register data. For more information about Macrovision video anticopy processes, please contact nearest MITSUBISHI Electric sales office. The video anticopy specification is provided to only those customers of MITSUBISHI Electric Corp. who have executed a license or a non-disclosure agreement with Macrovision Corp. Sample request and sales orders require the following procedure. In the case of the customers who have no license. Contact VP sales & marketing,ACP-PPV, Macrovision Corporation. Phone : USA (408) 743-8600 Fax : USA (408) 743-8610 Complete the appropriate agreement with Macrovision. Then, inform to MITSUBISHI in writing that the agreement has completed.
Timing Signal Generation
A number of internal timing signals are generated with the trailing edge of sync signals (shown in 4.2.1) as reference. All signals can be adjusted in 13.5MHz-step up to 1.2ms with respect to the reference sync signal.
8
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Composite-sync Generation
The timing-corrected c-sync signal, for an addition to the Y signal, is generated in accordance with RS170A (NTSC) and CCIR (PAL) standards, as shown in fig. 4.
IRE 133 100 90 0.714V
peak level including chroma signal white peak level
0H(reference point)
10.90.2s Equalizing pulse 9.40.1s 1.50.1s Serrated pulse
20
4 0 0.286V -40
4.70.1s 19 cycles 0.140.1s
40 2
set-up 7.52 0.140.2s 0.140.2s 2.30.1s 31.7775s 27.1s 0.140.2s 0.140.2s 4.70.1s 31.7775s
9 cycles
837 cycle counts (13.5MHz)
0 858
63 72
106127
0 31 429 460 cycle counts (13.5MHz)
0 429
366 795
Fig. 4-1 NTSC HORIZONTAL SYNC SIGNAL (referred to EIARS170A)
IRE 133 100 90 0.7V
50
peak level including chroma signal white peak level
0H(reference point)
120.3s 5.60.1s 1.50.3s set-up 0-2 0.20.1s 0.20.1s 2.350.1s 62.0s 27.3s 0.20.1s 0.20.1s 4.70.2s 62.0s Equalizing pulse Serrated pulse
10 0 0.3V -43 0.30.1s
4.70.2s
43 10%
101cycles 0.20.1s
844 cycle counts (13.5MHz)
0 864
63 76
107142
0 32 432 464 cycle counts (13.5MHz)
0 432
368 800
Fig. 4-2 PAL HORIZONTAL SYNC SIGNAL (referred to CCIR)
Serial Interface
The M65675FP/M65676FP has a serial data receiver, in compliance with both typical and high speed modes, based on I 2C serial bus specification. The slave-address of it also responds to two addresses of 40h and 42h. The address setting is done by following procedure; address setting pin DVASEL (pin 3) is "L" and "H" for the address of 40h and 42h, respectively. The serial data are stored in the data register in the serial interface block according to the appointed address after the receipt of the
data. The stored data will be loaded to the registers in each internal blocks at the timing of the first trailing edge of V-sync after the transmission flag (WE) have been set up.
Analog Blocks D-A Converter
The M65675FP/M65676FP has two 10-bit D-A converters. A reference current of the D-A converters is supplied directly through the Yref and Cref pins. The power save mode cuts the circuit current. The maximum output amplitude is 1.2VP-P.
9
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Y and C Mixing Circuit
The analog outputs of D-A converters are filtered and then input to the M65675FP again. The Y and C signals, whose maximum amplitude is 0.6VP-P, are combined and the resulting composite signal (CVBS) is output. The maximum amplitude of CVBS output is 1.2VP-P.
Operating Description Initialize
After power-on, the M65675FP/M65676FP has two different initialize sequences in the master and slave modes, respectively. In the master mode, the internal registers are initialized responding to the reset signal. After reset, the serial registers are set to the default data and an internal control clock (13.5MHz) is generated from the system clock. In the slave mode, the internal registers are initialized the same as in the master mode. The serial registers are set up to the default data and the system clock generates the internal control clock (13.5 MHz) in the synchronization with the trailing edge of the horizontal sync signal (H-sync), after reset. (Referring to Fig. 5) In case the serial registers are set up to data other than the default ones, the data should be renewed according to the I 2C bus format in both the master and slave modes, after reset.
6-dB Amplifier
The M65675FP has three 6-dB amplifiers. The maximum input is 0.6VP-P and the resulting maximum output will be 1.24VP-P. The maximum drivability and band width are 1mA and 6MHz, respectively.
*In the master modeO
System clock (27.0MHz)
Reset
H-sync
Generation starting timing of reference clock
*In the slave modeO
System clock (27.0MHz)
Reset
H-sync
Generation starting timing of reference clock
Fig. 5 GENERATION STARTING TIMING OF INTERNAL REFERENCE CLOCK
10
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Serial Register
The serial address register can be addressed by I 2C bus. The M65675FP/M65676FP has two slave addresses, 40 and 42h. In the actual use, one of two is selected and then Pin 3 (DVASEL) is set according to the selected address data
Slave address=40h 42h
bit7 0 0
bit6 1 1
bit5 0 0
bit4 0 0
bit3 0 0
bit2 0 0
bit1 0 1
bit0 R/W R/W
Register Mapping and Description
sub address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C CGMS/WSS 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 1 Macrovision OSD control CTY13 CTB13 CTR13 CTY33 CTB33 CTR33 CTY53 CTB53 CTR53 CTY12 CTB12 CTR12 CTY32 CTB32 CTR32 CTY52 CTB52 CTR52 CTY11 CTB11 CTR11 CTY31 CTB31 CTR31 CTY51 CTB51 CTR51 Write control Interface Sync level Burst level Sync delay Y delay TINT Closed Caption (1st field) Closed Caption (2nd field) Function data 7 WE 525/ 625 CC1F sync7 6 P-save 5 UVin 2 Color YCINV CbCrINV Bar SCH CCD1 sync4 burst4 SD4 YD4 TINT4 CC104 CC114 CC204 CC214 CG05/ WS04 CG13/ WS12 CLTEN CTY10 CTB10 CTR10 CTY30 CTB30 CTR30 CTY50 CTB50 CTR50 offset CCD0 sync3 burst3 SD3 YD3 TINT3 CC103 CC113 CC203 CC213 CG04/ WS03 CG12/ WS11 OSD CLK CTY03 CTB03 CTR03 CTY23 CTB23 CTR23 CTY43 CTB43 CTR43 CTY63 CTB63 CTR63 N0 [3] N1 [3] N2 [3] N3 [3] N4 [3] N6 [0] 4 3 1 0
NTSC/ PAL YC/UV CC2F sync6 burst6 CCI/F sync5 burst5
Setup1 Setup0 CCIR1 CCIR0 sync2 sync1 burst2 SD2 YD2 TINT2 CC102 CC112 CC202 CC212 CG03/ WS02 CG11/ WS10 BLD mode CTY02 CTB02 CTR02 CTY22 CTB22 CTR22 CTY42 CTB42 CTR42 CTY62 CTB62 CTR62 N0 [2] N1 [2] N2 [2] N3 [2] N4 [2] N5 [2] burst1 SD1 YD1 TINT1 CC101 CC111 CC201 CC211 CG02/ WS01 CG10/ WS09 BLD1 CTY01 CTB01 CTR01 CTY21 CTB21 CTR21 CTY41 CTB41 CTR41 CTY61 CTB61 CTR61 N0 [1] N1 [1] N2 [1] N3 [1] N4 [1] N5 [1]
CGMS /WSS sync0 burst0 SD0 YD0 TINT0 CC100 CC110 CC200 CC210 CG01/ WS00 CG09/ WS08 BLD0 CTY00 CTB00 CTR00 CTY20 CTB20 CTR20 CTY40 CTB40 CTR40 CTY60 CTB60 CTR60 N0 [0] N1 [0] N2 [0] N3 [0] N4 [0] N5 [0]
TINT6 CC106 CC116 CC206 CC216 CG08/ CG07/ WS07 WS06
TINT7
TINT5 CC105 CC115 CC205 CC215 CG06/ WS05 CG14/ WS13
Color Lookup Table
Mode selection Color Stripe Definition #1 Color Stripe Definition #2 Color Stripe Definition #3 Color Stripe Definition #4 Color Stripe Definition #5/6/7
N16 [0] N0 [6]
N0 [5]
N0 [4] N1 [4] N2 [4] N3 [4] N4 [4] N6 [1]
N21 [1] N21 [0] N1 [5] N2 [5] N3 [5] N4 [6] N7 [1] N7 [0] N4 [5] N6 [2]
11
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Register Mapping and Description (cont.)
sub address 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D
*1 : These registrs are M65675FP only
Function Pseudo-sync parameter #1 Pseudo-sync parameter #2 Pseudo-sync parameter #3 Pseudo-sync/AGC pulse line select Pseudo-sync/AGC pulse A/B select 1 Macrovision Pseudo-sync/AGC on/off FormatA Pseudo-sync/AGC on/off FormatB
data 7 6 5 N8 [5] N9 [5] 4 N8 [4] N9 [4] 3 N8 [3] N9 [3] 2 N8 [2] N9 [2] 1 N8 [1] N9 [1] 0 N8 [0] N9 [0]
N10 [5] N10 [4] N10 [3] N10 [2] N10 [1] N10 [0] N11 [7] N11 [6] N11 [5] N11 [4] N11 [3] N11 [2] N11 [1] N11 [14] N11 [13] N11 [12] N11 [11] N11 [10] N11 [9] N12 [7] N12 [6] N12 [5] N12 [4] N12 [3] N12 [2] N11 [1] N12 [14] N12 [13] N12 [12] N12 [11] N12 [10] N12 [9] N11 [0] N11 [8] N12 [0] N12 [8]
N13 [7] N13 [6] N13 [5] N13 [4] N13 [3] N13 [2] N13 [1] N13 [0] N14 [7] N14 [6] N14 [5] N14 [4] N14 [3] N14 [2] N14 [1] N14 [0]
Back Porch pulse N15 [7] N15 [6] N15 [5] N15 [4] N15 [3] N15 [2] N15 [1] N15 [0] configuration Start to 1st/1st to 2nd N18 [3] N18 [2] N18 [1] N18 [0] N17 [3] N17 [2] N17 [1] N17 [0] Phase Switch Point 2nd to End Phase Switch Point/ Subcarrier Phase Colorstripe line phase N20 [2] N20 [1] N20 [0] N19 [3] N19 [2] N19 [1] N19 [0] N21 [9] N21 [8] N21 [7] N21 [6] N21 [5] N21 [4] N21 [3] N21 [2]
Register Functional Description
Sub address WE Name Function Register Write Enable "0" write disable "1" write enable Power Down Control "0" power down "off" "1" power down "on" Input Video Data Format Selection "0" Y/U/V input "1" Y/Cb/Cr input Pixel Data Sep. Timing Control (Y/C) "0" Y/C separation in inverted timing "1" Y/C separation in non-inverted timing Pixel Data Sep. Timing Control (Cb/Cr) "0" Y/C separation in inverted timing "1" Y/C separation in non-inverted timing Color Bar Generation Control "0" color bar generation "off" "1" color bar generation "on" Input Pixel Data Field Frequency Setting "0" 525/60 field "1" 625/50 field Line Phase Inversion Control in V-axis "0" Phase Inversion "off" (NTSC) "1" Phase Inversion "on" (PAL) Selection of DAC Output "0" Y/C output "1" U/V output SCH Phase Control "0" SCH Phase Control "on" "1" SCH Phase Control "off" Remark Default Data
P-save
UVin 00 Y/CINV
20h
Cb/CrINV
Color Bar
Color look-up table should be initialized.
525/625
NTSC/PAL 01 YC/UV
03h
SCH
12
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
Register Functional Description (cont.)
Sub address Name offset Function fsc Offset Frequency (25Hz) Control "0" offset no-addition "1" offset addition 7.5IRE Setup Control "00" setup "off" "01" +7.5IRE setup "1X" -7.5IRE setup CGMS/WSS Generation Control "0" CGMS/WSS generation "off" "1" CGMS/WSS generation "on" Closed Caption Data Transmission Flag in Field 1. Closed Caption Data Transmission Flag in Field 2. Closed Caption Interface Setting "0" internal generation mode "1" external input mode Closed Caption Generation Setting "00" generation "off" "01" generation for only field 1 "10" generation for only field 2 "11" reserved Input Pixel Data Format Setting "00" CCIR656 "01" 8bit CCIR601 "10" 16bit CCIR601 "11" reserved Sync Signal Output Level Setting Burst Level Setting Composite Sync Multiplexing Timing Setting Luma Signal Delay Setting Chroma Output TINT Control 1st Byte Data Setting for Field 1 2nd Byte Data Setting for Field 1 1st Byte Data Setting for Field 2 2nd Byte Data Setting for Field 2 CGMS or WSS Data Setting CLT Data Renewing Enable "0" disable "1" enable OSDCLK Frequency Setting "0" 6.75MHz "1" 13.5MHz Blending Mode Setting "0" Y and C are mixing "1" Only Y is mixing Blending Color Address Setting "00" blending "off" "01" CLT0 is set for a blending color "10" CLT(1:0) is set for a blending Color "11" CLT(2:0) is set for a blending color Color Look-up table RAM Setting Remark It have to set "1" in the setting of 525/625=0 It is active in the setting of 525/625=0. CGMS/WSS selection is depend on 525/62 setting. 03h Default Data
01
setup (1:0)
CGMS/WSS CC1F CC2F 02 CCI/F
CCD (1:0) 02 CCIR (1:0)
00h
03 04 05 06 07 08 09 0A 0B 0C : 0D
sync (7:0) burst (6:0) SD (4:0) YD (4:0) TINT (7:0) CC10 (6:0) CC11 (6:0) CC20 (6:0) CC21 (6:0) CG (14:1) [WS (13:0)] CLTEN
DBh 54h 19h 04h 00h 00h 00h 00h 00h 00h
00h
0E
OSDCLK
00h In the case of "1", C is equal to the OSD setting color.
BLD mode
00h
0E
BLD (1:0)
00h
0F : 1A 1B : 2D
CTY (00:63) CTB (00:63) CTR (00:63) N0 : N21
00h
Macrovision Setting
00h
13
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
DESCRIPTION OF PIN
Pin No. 1 2 Pin name DVSS2 PXCLK Type Supply Digital ground for I/O. O Function
Reference clock for pixel data input. The clock frequency is 27.0MHz or 13.5MHz in CCIR656/8-bit CCIR601 or 16-bit CCIR601 input mode, respectively. I2C slave address setting. "Low" is for the slave address of 40h. "High" is for the slave address of 42h. Horizontal sync signal. It is an input or output in the slave or master mode, respectively. Vertical sync signal. It is an input or output in the slave or master mode, respectively.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
DVASEL HD VD VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 DVSS2 DVDD2 DVDD1 DVSS1 OSDCK OSD0 OSD1 OSD2 Master/Slave RESET ACK SDA SCL TEST DVDD1 N.C. N.C. C N.C. CVBS AVSS2 Y AVDD2 Yin N.C. Cin
I I/O I/O
I/O
Video data inputs. The input video data are the luma (Y) data as defined in CCIR Rec 601 in 16-bit CCIR601 mode. In the Y/U/V output mode, the output is 10-bit luma signal with a composite sync. In 16-bit CCIR601 mode, an MSB and LSB is VD7 and VD0, and in the Y/U/V output mode, VD9 and VD0, respectively.
Supply Supply Supply Supply O
Digital ground for I/O. Digital positive supply for I/O. Digital positive supply for internal logic. Digital Ground for internal logic. Reference clock for the external OSD microprocessor. The frequency is 13.5MHz or 6.25MHz, alternated by I 2C bus control. Color Look-up table address input. MSB and LSB is OSD2 and OSD0, respectively. Synchronizing mode selection. "Low" is for the slave mode. "High" is for the master mode. Asynchronous reset, active "LOW". Acknowledge line (Open drain output). Serial data line/Acknowledge line (Open drain output). Serial clock line.
I
I I O I/O I I
Test mode control. It should be grounded during actual use. Supply Digital positive supply for internal logic. No connection. No connection. The analog chroma output signal from 6-dB amplifier. The output amplitude is 1.0VP-P (typ.), while the input one is 0.5VP-P. No connection. The analog composite video output signal from 6-dB amplifier. O The output amplitude is 1.24VP-P (typ.). Supply Analog ground for 6-dB amplifiers. O The analog luma output signal from 6-dB amplifier. The output amplitude is 1.2VP-P (typ.), while the input one is 0.6VP-P. Supply Analog positive supply for 6-dB amplifiers. O I The analog luma input from an external LPF. This input has clamp circuit. The signal must input via capacitor. No connection The analog chroma input from an external LPF. This input has bias circuit. The signal must input via capacitor.
I
14
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
DESCRIPTION OF PIN (cont.)
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name Ccomp DAC AVDD1 AVSS1 DAY Cref Yref Ycomp N.C. DVDD1 DVSS1 Xout Xin DVSS2 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 DVDD2 Type Function Phase compensation for chroma or V D/A converters. I It should be connected to the analog ground via a capacitor. Chroma or V signal output. O It should be connected to the analog supply via a resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. Supply Analog positive supply for D/A converters. Supply Analog ground for D/A converters. Luma or V signal output. O It should be connected to the analog supply via a resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. I I I Reference current control for chroma or V D/A converter. It should be connected to the analog supply via a reference resistor (Rref). Reference current control for luma or U D/A converter. It should be connected to the analog supply via a reference resistor (Rref).
Phase compensation for luma or U D/A converters. It should be connected to the analog ground via a capacitor. No connection. Supply Digital positive power supply for internal logic. Supply Digital ground for internal logic. O I System clock output. It should be in no connection except that it is connected to a X'tal oscillator.
System clock input. The clock frequency is 27.0MHz only. Supply Digital ground for I/O.
I
Pixel data inputs. The acceptable video data are; multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV as defined in CCIR Rec656, and multiplexed video data (Y/Cb/Cr) as defined in CCIR Rec601, and multiplexed Color difference signals (Cb/Cr). An MSB and LSB is PXD7 and PXD0, respectively.
Supply Digital positive power supply for I/O
Interface
The M65675FP/M65676FP has two interfaces as follows; Pixel data interface OSD interface
M65675FP/M65676FP through PXDATA [7:0] ports synchronizing with a pixel clock (PXCLK) generated by the LSI. In the case of CCIR601 16-bit serial data, 8-bit color difference signals (Cb/Cr or U/V) and luma signal (Y) are taken into the LSI synchronizing with pixel clock (PXCLK) through PXD [7:0] and VD [7:0] port, respectively. CCIR656 pixel data are accepted in only the slave mode, while CCIR601 ones are accepted in both the master and slave modes. In the case of CCIR656 pixel data, H/V sync and a field identification signals are regenerated internally referring to SAV and EAV code multiplexed in the pixel data. In the case of CCIR601 pixel data, H/V sync and the field identification signals are regenerated internally, then the H and V sync signals are available via HD and VD ports in the master mode operation, respectively. Moreover, in the slave mode, the M65675FP/M65676FP is in the slave operation synchronized with H/V sync signals via HD/VD ports and a field identification is done using the H/V sync input signals.
Pixel Data Interface
The M65675FP/M65676FP accepts these 6 digital pixel data formats as shown below; In CCIR656 Y and Cb/Cr, in a digital video transmission format Y and U/V, in a time multiplexed 8-bit serial data format In CCIR601 Y and Cb/Cr, in a digital video transmission format Y and U/V, in a time multiplexed 8-bit serial data format Y, in a digital video transmission format and time multiplexed Cb/Cr Y and U/V, in a time multiplexed 16-bit serial data format The 8-bit serial data in CCIR656 and CCIR601 are taken into the
15
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
The pixel data interface pin assignment is shown in Table 1.
Table 1 Pixel Data Interface Pin Assignment
Pin name PXCLK HD (Note1) VD (Note1) PXD [7:0] PD [7:0] I/O O I/O I/O I I Function Pixel clock output. In the case of CCIR656 / CCIR601 8-bit data and CCIR601 16-bit inputs, this will be a free-run clock of 27MHz and 13.5MHz, respectively. Horizontal sync signal. Input in the slave or output in the master mode. Vertical sync signal. Input in the slave or output in the master mode. Pixel data input. 8-bit data input in CCIR656 / CCIR601 or the color differential signals (Cb/Cr) input in CCIR601 16-bit data format. Pixel data input. Luma (Y) data input in CCIR601 16-bit data format.
Note1 : In CCIR656 mode, H sync and V sync generated by EAV will be output via terminals HD and VD, respectively.
OSD Interface
The OSD data, which are storaged in the address assigned by the color look-up table RAM (CLT-RAM) address data input via OSD [2:0] ports, are multiplexed into the Y signal synchronizing with OSD The OSD interface pin assignment is shown in Table 2. clock (OSDCK) delivered from the M65675FP/M65676FP.
Table 2 The OSD interface Pin assignment
Pin name OSDCK OSD [2:0] I/O O I Function OSD clock output. 13.5MHz free-run clock or 6.25MHz H-start-and-stop clock. Color look-up table RAM address input.
16
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65675FP/M65676FP
DIGITAL NTSC/PAL ENCODER
APPLICATION EXAMPLE
A typical application diagram of the M65675FP/M65676FP together with the M65773FP 1-chip MPEG2 decoder is shown in Figure 6.
CVBS 0.1F 75 220F
75 1k 2.2F 2.2F 0.1F 10k 0.1F 10k Filter Stage Filter Stage
DAC 300 C in 0.1F DAY
AVDD AVss Ccomp Ycomp Cref
Yref
Y in
2.2F
47F 0.01F
300
Y C CVBS
2.2F 0.1F 2.2F
220F 75
75 Driver
C
Y
TEST Master/Slave DVASEL DVSS 47F 0.01F DVDD X out X in VD(9:0)
Digital NTSC/PAL Encoder
M65675FP M65676FP
PXD(7:0) PXCLK
RESET OSD(2:0) OSDCK ACK SDA SCL
R/G/B OSC1
OSD micro computer Lch VD HD RESET CS SCK SIN Rch Units Resistance : Capacitance : F
M35041
27MHz
HD VD
Audio DAC DIN LRCIN BCKIN XTI
47F 0.01F
8
VSS VDD
CLK in
SCL SDA/ACK RESET AO0 MPEG2 AO1 System/ AO2 Video/Audio AO3 Decoder M65773FP LRCLK BCLK BDEN BDREQ DOCLK DACCLK ACLKO ACLKI
16M SDRAM
27MHz XO
HSYNC VSYNC
PXCLK
PXD
BDER
BD
3.3k 8
RCLK BDEN BDREQ
Chanel Decoder
: 3.3V Supply for Analog/Digital (Note 1) Connect a tantalum or electrolytic capacitor of 10F or more and a ceramic capacitor of 0.01F each in parallel between DVDD/AVDD and DVss/AVss pins. These capacitors should be placed as possible to the device. (Note 2) In case several LSIs are connected to an I2C bus, SDA and ACK at power-down should be tied externally in a situation when only M65675FP/M65676FP is power-off.
Fig. 6 TYPICAL APPLICATION DIAGRAM
17
RESET CS SCK SIN
BD
BDER
Host CPU
Audio out (R)
Audio out (L)
47F 0.01F VDD VSS
3

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